A buffer is a device included between two stages, an input and a load, which permits signal transfer from the input to the load so that, for example, changes in impedance in one stage have no effect on the performance of the other. Buffer circuits are often used in driving capacitive loads, in which the current at the load leads in phase the voltage at the load. A performance limitation of such buffer circuits is the ability to quickly switch large capacitively loaded networks from one voltage level to another. To achieve fast switching speeds for heavy loads, large source followers with current source pull-downs are usually employed, but they require considerable area and power. These prior art buffer configurations, including memory devices and GaAs MESFET (METAL SEMICONDUCTOR FIELD-EFFECT TRANSISTOR) integrated circuits, appear in several logic forms. For example, BFL (BUFFERED FET LOGIC) is described in R. Van Tuyl and C. Liechti, "High-Speed Integrated Logic with GaAs MESFET's", IEEE Journal of Solid-State Circuits, Vol. SC-9, No. 5, October 1974; SDFL (SCHOTTKY DIODE FET LOGIC) is described in R. Eden, B. M. Welch, and R. Zucca, "Low Power GaAs Digital ICs Using Schottky Diode-FET Logic", ISSCC Digest of Technical Papers, p. 68, Feb. 15, 1978; and SCFL (SOURCE COUPLED FET LOGIC) is described in S. Katsu, S. Nambu, S. Shimano, and G. Kano, "A GaAs Monolithic Frequency Divider Using Source Coupled FET Logic", IEEE Electron Device Letters, Vol. Ed 1-3, No. 8, August 1982. In these logic forms, the principal components of each buffering element are two depletion mode MESFETs (which depending on the logic form may also include level shifting diodes) comprising a source follower and a current source pull-down. These buffers are designed using two MESFETs with channels having sufficient width to drive a load capacitance. A limitation to this design, however, is that large MESFETs are required for large loads, thus utilizing high static power and taking up significant area on the chip.